1. Field of the Invention
This invention relates to a semiconductor device and a method of making the same, and more particularly to a semiconductor device capable of reducing affects induced through a substrate or a buffer layer to an epitaxially grown layer such as an active layer grown thereon, and a method of making the same.
2. Description of the Related Art
Recently, novel electronic devices and optoelectronic devices are realized by growing epitaxial layers on a single crystal semiconductor substrate. The epitaxial layers consist of multilayer structure or supperlattice structure which require sophisticated control of doping and compositional profiles.
Molecular beam epitaxy (MBE), and metalorganic vapor phase epitaxy (MOVPE) have emerged as important and matured epitaxial growth for these devices.
When such a GaAs/n-AlGaAs hetero junction (or maltilayer structure) is grown in that a non-doped GaAs layer and a Si-doped AlGaAs layer form a hereto junction, a two dimensional electron gas (2 DEG) having a high electron mobility is generated at the hereto junction on the GaAs side. Field effect transistor (FET) having this 2 DEG layer as a channel layer is called high electron mobility transistor (HEMT).
The HEMT is one of the novel electronic devices realized by utilizing epitaxial growth technique. In these electronic devices, it is very important to enable control of electric characteristics of a channel or an active layer, and further to enable control of crystalinity at both a buffer layer and the interface between a substrate and the buffer layer. Thus, epitaxial growth technique capable of such control should be explored.
According to the conventional method of manufacturing HEMT, a wafer for making HEMT is made by growing an undoped GaAs layer having a thickness, for example, of 0.5-1.0 .mu.m on a GaAs substrate and a Si-doped AlGaAs layer on the GaAs epitaxial layer, by MBE or MOVPE.
HEMT's are manufactured by processing this wafer. First, those portions of the wafer where gate electrodes are to be formed are subjected to dry etching to reduce the thickness of the Si-doped n-type AlGaAs to a predetermined value. Then, AuGe/Au laminated layers are formed on the wafer by physical deposition, patterned by photolithography, and alloyed to form ohmic source and drain electrodes on the both sides of each gate electrode portion.
Then, a resist mask having an aperture at each gate electrode portion is formed on the wafer. An aluminum electrode layer is deposited in vacuum and lifted off by the resist removal to form aluminum gate electrode at the gate electrode portion. HEMT structures are manufactured in this way.
When HEMT's are formed in an integrated circuit, such side gate effect (or back gate effect) is known to occur that adjacent devices interfere mutually.
For example, assume that a device A and a device B are located adjacent to each other and isolated by an isolation region formed by implanting oxygen ions into the wafer. When a voltage (side gate voltage) is applied between the source electrode of the device A and a certain electrode (side gate) of the device B, a leak current may be allowed to flow through the device A. As a result, the threshold voltage Vth of the device A varies. This phenomenon is the side gate effect.
The reason of this phenomenon can be considered as follows. There may exist interface levels in the neighborhood of the interface between the substrate and the epitaxially grown layer due to impurities, etc, or impurity levels in the buffer layer. Electrons or holes trapped at these levels can be excited by a high electric field to produce an electric current. When this electric field is originated by the voltage application in the adjacent device, the current may flow in a device not intended.
The present inventor and his colleague has found and reported that the side gate effect in the HEMT integrated circuit can be reduced by reducing impurities existing in the neighborhood of the interface between the substrate and the epitaxially grown layer.
Reference may be made to (1) T. Yokoyama et al "Reduction of Backgating Effect in HEMT's" IEEE Electron Device Letters. Vol. EDL-8, No.6, June 1987, pp 280-281, and (2) J. Saito et al "Effect of Thermal Etching on GaAs Substrate in Molecular Beam Epitaxy" Japan. J. Appln. Phys. Vol. 25, No.8, 1986, pp 1216-1220, which are incorporated herein by reference.
According to this technique, a GaAs substrate is heated to or above 750.degree. C. under the irradiation of arsenic (As) molecular beam before crystal growth by MBE, to thermally etch the surface of the GaAs substrate by about 200-300 A. Residual impurities on the surface, such as carbon, can be removed by this thermal etching. Then, GaAs/n-AlGaAs hereto structure is formed on the cleaned GaAs substrate surface by MBE.
If epitaxial growth by MBE is done without thermal etching, residual impurities such as carbon on GaAs substrate surface may be incorporated into the epitaxially grown GaAs layer. As a result, shallow impurity levels can be produced the neighborhood of the interface between the substrate and the epitaxially grown layer.
The present inventor and his colleague have confirmed that such shallow impurity is mainly carbon (e.g. see above-mentioned article (2)). Carbon atoms produce acceptor levels by occupying As sites in the GaAs crystal. When there exist acceptor levels in a HEMT integrated circuit, a leak current can flow through the neighborhood of the interface between the substrate and the epitaxially grown layer by the application of a side gate voltage to a side gate electrode. Thus, variation of the threshold voltage can arise due to the side gate effect.
It is also confirmed that when HEMT's are made by cleaning the substrate surface by thermal etching and then performing epitaxial growth, the threshold voltage does not vary up to a side gate voltage of 60 V, when the distance to a side gate electrode is 100 .mu.m (e.g. see above-mentioned article (1)).
A method of using a buffer layer grown at a low temperature is known to be effective for reducing the side gate effect (for example, see (3) F. W. Smith et al "New MBE Buffer Used to Eliminate Backgating in GaAs MESFET's" IEEE Electron Device Letters, Vol. 9, No. 2, Feb. 1988, pp 77-80).
According to this method, in the case of growing epitaxial layer structure for forming GaAs MESFET on GaAs substrate by MBE, first GaAs buffer layer is grown at a low temperature of 150.degree. to 300.degree. C., and then an n type GaAs active layer is grown thereon at a normal growth temperature of about 600.degree. C.
In the MESFET's formed by using the epitaxial layer structure grown as described above, the threshold voltage of the MESFET does not change up to a side gate voltage of 30 V when the distance to a side gate electrode is 50 .mu.m. Thus, the side gate effect can be reduced (e.g. see above-mentioned article (3)). Joint research group of IBM and Purdue University explains the reason of reducing the side gate effect by the use of epitaxial growth structure formed on a buffer layer grown at a low temperature as follows. In the GaAs buffer layer grown at a low temperature, arsenic (As) precipitates having a diameter of 20-100 A exist at a density above 10.sup.17 cm.sup.-3. Buried Schottky barriers, which are metal-semiconductor interfaces, are formed in the GaAs layer by the existence of these As precipitates. Depletion layers due to these Schottky barriers extend throughout the GaAs layer and are connected to each other to exhibit high resistivity. (see (4) M. R. Melloch et al "Formation of Arsenic Precipitates in GaAs Buffer Layers Grown by Molecular Beam Epitaxy at Low Substrate Temperatures" Appl. Phys. Lett. Vol. 57 (1990) pp 1531-1533, (5) A. C. Warren et al "Arsenic Precipitates and the Semi-insulating Properties of GaAs Buffer layers Grown by Low Temperature Molecular Beam Epitaxy" Appl. Phys. Lett. Vol. 57 (1990) pp 1331-1333, and (6) M. R. Melloch et al "GaAs Buffer Layers Grown at Low Substrate Temperatures Using As.sub.2 and the Formation of Arsenic Precipitates" Journal of Crystal Growth, Vol.111 (1991) pp 39-42.
It is not easy to control the process of first cleaning substrate surface by thermal etching and then performing epitaxial growth to reduce the side gate effect. That is, since GaAs substrate is heated to a high temperature of 750.degree. C., dissociation of As selectively occurs simultaneously with the etching. Thus, surface morphology is degraded with the increase of etching, to produce surface roughness.
Normally, the etch rate in this case is about 70-100 A/min, when As pressure is 1.5.times.10.sup.-5 torr. The each rate is dependant on the pressure of irradiating As beam. Reduction of the side gate effect is obtained when the etched amount is about 200-300 A. When etching is done deeper than this value, the surface morphology is degraded and manufacture of an integrated circuit becomes difficult.
According to the method of manufacturing an integrated circuit by first growing a buffer layer at a low temperature and then growing epitaxial layers thereon, it is necessary to first set the substrate temperature at a very low temperature of 150.degree.-300.degree. C. to grow a buffer layer, compared to 600.degree. C. which is the ordinary substrate temperature for growing GaAs layer. This means that relatively long time is required for raising the substrate temperature after cleaning. Also, it is not easy to accurately control such a low temperature.